/*
 * Copyright (C) 2017 Spreadtrum Communications Inc.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2017-12-14 16:29:53
 *
 */


#ifndef REG_FW0_AON_H
#define REG_FW0_AON_H

#define CTL_BASE_REG_FW0_AON 0x32804000


#define REG_REG_FW0_AON_REG_RD_CTRL_0          ( CTL_BASE_REG_FW0_AON + 0x0000 )
#define REG_REG_FW0_AON_REG_RD_CTRL_1          ( CTL_BASE_REG_FW0_AON + 0x0004 )
#define REG_REG_FW0_AON_REG_RD_CTRL_2          ( CTL_BASE_REG_FW0_AON + 0x0008 )
#define REG_REG_FW0_AON_REG_RD_CTRL_3          ( CTL_BASE_REG_FW0_AON + 0x000C )
#define REG_REG_FW0_AON_REG_RD_CTRL_4          ( CTL_BASE_REG_FW0_AON + 0x0010 )
#define REG_REG_FW0_AON_REG_RD_CTRL_5          ( CTL_BASE_REG_FW0_AON + 0x0014 )
#define REG_REG_FW0_AON_REG_WR_CTRL_0          ( CTL_BASE_REG_FW0_AON + 0x0018 )
#define REG_REG_FW0_AON_REG_WR_CTRL_1          ( CTL_BASE_REG_FW0_AON + 0x001C )
#define REG_REG_FW0_AON_REG_WR_CTRL_2          ( CTL_BASE_REG_FW0_AON + 0x0020 )
#define REG_REG_FW0_AON_REG_WR_CTRL_3          ( CTL_BASE_REG_FW0_AON + 0x0024 )
#define REG_REG_FW0_AON_REG_WR_CTRL_4          ( CTL_BASE_REG_FW0_AON + 0x0028 )
#define REG_REG_FW0_AON_REG_WR_CTRL_5          ( CTL_BASE_REG_FW0_AON + 0x002C )
#define REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY0   ( CTL_BASE_REG_FW0_AON + 0x0030 )
#define REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY1   ( CTL_BASE_REG_FW0_AON + 0x0034 )
#define REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY2   ( CTL_BASE_REG_FW0_AON + 0x0038 )
#define REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY3   ( CTL_BASE_REG_FW0_AON + 0x003C )
#define REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY4   ( CTL_BASE_REG_FW0_AON + 0x0040 )
#define REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY5   ( CTL_BASE_REG_FW0_AON + 0x0044 )
#define REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY6   ( CTL_BASE_REG_FW0_AON + 0x0048 )
#define REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY7   ( CTL_BASE_REG_FW0_AON + 0x004C )
#define REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY8   ( CTL_BASE_REG_FW0_AON + 0x0050 )
#define REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY9   ( CTL_BASE_REG_FW0_AON + 0x0054 )
#define REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY10  ( CTL_BASE_REG_FW0_AON + 0x0058 )
#define REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY11  ( CTL_BASE_REG_FW0_AON + 0x005C )
#define REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY12  ( CTL_BASE_REG_FW0_AON + 0x0060 )
#define REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY13  ( CTL_BASE_REG_FW0_AON + 0x0064 )
#define REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY14  ( CTL_BASE_REG_FW0_AON + 0x0068 )
#define REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY15  ( CTL_BASE_REG_FW0_AON + 0x006C )
#define REG_REG_FW0_AON_BIT_CTRL_ARRAY0        ( CTL_BASE_REG_FW0_AON + 0x0070 )
#define REG_REG_FW0_AON_BIT_CTRL_ARRAY1        ( CTL_BASE_REG_FW0_AON + 0x0074 )
#define REG_REG_FW0_AON_BIT_CTRL_ARRAY2        ( CTL_BASE_REG_FW0_AON + 0x0078 )
#define REG_REG_FW0_AON_BIT_CTRL_ARRAY3        ( CTL_BASE_REG_FW0_AON + 0x007C )
#define REG_REG_FW0_AON_BIT_CTRL_ARRAY4        ( CTL_BASE_REG_FW0_AON + 0x0080 )
#define REG_REG_FW0_AON_BIT_CTRL_ARRAY5        ( CTL_BASE_REG_FW0_AON + 0x0084 )
#define REG_REG_FW0_AON_BIT_CTRL_ARRAY6        ( CTL_BASE_REG_FW0_AON + 0x0088 )
#define REG_REG_FW0_AON_BIT_CTRL_ARRAY7        ( CTL_BASE_REG_FW0_AON + 0x008C )
#define REG_REG_FW0_AON_BIT_CTRL_ARRAY8        ( CTL_BASE_REG_FW0_AON + 0x0090 )
#define REG_REG_FW0_AON_BIT_CTRL_ARRAY9        ( CTL_BASE_REG_FW0_AON + 0x0094 )
#define REG_REG_FW0_AON_BIT_CTRL_ARRAY10       ( CTL_BASE_REG_FW0_AON + 0x0098 )
#define REG_REG_FW0_AON_BIT_CTRL_ARRAY11       ( CTL_BASE_REG_FW0_AON + 0x009C )
#define REG_REG_FW0_AON_BIT_CTRL_ARRAY12       ( CTL_BASE_REG_FW0_AON + 0x00A0 )
#define REG_REG_FW0_AON_BIT_CTRL_ARRAY13       ( CTL_BASE_REG_FW0_AON + 0x00A4 )
#define REG_REG_FW0_AON_BIT_CTRL_ARRAY14       ( CTL_BASE_REG_FW0_AON + 0x00A8 )
#define REG_REG_FW0_AON_BIT_CTRL_ARRAY15       ( CTL_BASE_REG_FW0_AON + 0x00AC )

/* REG_REG_FW0_AON_REG_RD_CTRL_0 */

#define BIT_REG_FW0_AON_AON_CHIP_ID_RD_SEC                 BIT(31)
#define BIT_REG_FW0_AON_AON_VER_ID_RD_SEC                  BIT(30)
#define BIT_REG_FW0_AON_AON_MFT_ID_RD_SEC                  BIT(29)
#define BIT_REG_FW0_AON_AON_IMPL_ID_RD_SEC                 BIT(28)
#define BIT_REG_FW0_AON_AON_PLAT_ID1_RD_SEC                BIT(27)
#define BIT_REG_FW0_AON_AON_PLAT_ID0_RD_SEC                BIT(26)
#define BIT_REG_FW0_AON_AON_CHIP_ID1_RD_SEC                BIT(25)
#define BIT_REG_FW0_AON_AON_CHIP_ID0_RD_SEC                BIT(24)
#define BIT_REG_FW0_AON_AP_AXI_CTRL_RD_SEC                 BIT(23)
#define BIT_REG_FW0_AON_AUTO_GATE_CTRL1_RD_SEC             BIT(22)
#define BIT_REG_FW0_AON_AUTO_GATE_CTRL0_RD_SEC             BIT(21)
#define BIT_REG_FW0_AON_MDAR_SYS_HSDL_CFG_RD_SEC           BIT(20)
#define BIT_REG_FW0_AON_CM4_SYS_SOFT_RST_RD_SEC            BIT(19)
#define BIT_REG_FW0_AON_USER_RSV_FLAG1_RD_SEC              BIT(18)
#define BIT_REG_FW0_AON_DAP_DJTAG_SEL_RD_SEC               BIT(17)
#define BIT_REG_FW0_AON_AON_APB_CLK_SEL_RD_SEC             BIT(16)
#define BIT_REG_FW0_AON_AON_REG_PROT_RD_SEC                BIT(15)
#define BIT_REG_FW0_AON_AUDCP_BOOT_PROT_RD_SEC             BIT(14)
#define BIT_REG_FW0_AON_DCXO_LC_REG1_RD_SEC                BIT(13)
#define BIT_REG_FW0_AON_DCXO_LC_REG0_RD_SEC                BIT(12)
#define BIT_REG_FW0_AON_CP_ARM_JTAG_CTRL_RD_SEC            BIT(11)
#define BIT_REG_FW0_AON_BB_BG_CTRL_RD_SEC                  BIT(10)
#define BIT_REG_FW0_AON_BOOT_MODE_RD_SEC                   BIT(9)
#define BIT_REG_FW0_AON_TS_CFG_RD_SEC                      BIT(8)
#define BIT_REG_FW0_AON_PWR_CTRL_RD_SEC                    BIT(7)
#define BIT_REG_FW0_AON_APB_RTC_EB0_RD_SEC                 BIT(6)
#define BIT_REG_FW0_AON_APB_RST2_RD_SEC                    BIT(5)
#define BIT_REG_FW0_AON_APB_RST1_RD_SEC                    BIT(4)
#define BIT_REG_FW0_AON_APB_RST0_RD_SEC                    BIT(3)
#define BIT_REG_FW0_AON_APB_EB2_RD_SEC                     BIT(2)
#define BIT_REG_FW0_AON_APB_EB1_RD_SEC                     BIT(1)
#define BIT_REG_FW0_AON_APB_EB0_RD_SEC                     BIT(0)

/* REG_REG_FW0_AON_REG_RD_CTRL_1 */

#define BIT_REG_FW0_AON_EB_AON_ADD1_RD_SEC                 BIT(31)
#define BIT_REG_FW0_AON_VDSP_INT_CTRL_RD_SEC               BIT(30)
#define BIT_REG_FW0_AON_SOFT_RST_AON_ADD1_RD_SEC           BIT(29)
#define BIT_REG_FW0_AON_ESE_INT_MASK_RD_SEC                BIT(28)
#define BIT_REG_FW0_AON_AON_SOC_USB_CTRL_RD_SEC            BIT(27)
#define BIT_REG_FW0_AON_PUBCP_LPC_CTRL_RD_SEC              BIT(26)
#define BIT_REG_FW0_AON_WTLCP_LPC_CTRL_RD_SEC              BIT(25)
#define BIT_REG_FW0_AON_VECTOR_VDSP_RD_SEC                 BIT(24)
#define BIT_REG_FW0_AON_PUBCP_CTRL_RD_SEC                  BIT(23)
#define BIT_REG_FW0_AON_PCP_SOFT_RST_RD_SEC                BIT(22)
#define BIT_REG_FW0_AON_PCP_AON_EB_RD_SEC                  BIT(21)
#define BIT_REG_FW0_AON_WTL_WCDMA_EB_RD_SEC                BIT(20)
#define BIT_REG_FW0_AON_WTLCP_CTRL_RD_SEC                  BIT(19)
#define BIT_REG_FW0_AON_WTLCP_TDSP_CTRL1_RD_SEC            BIT(18)
#define BIT_REG_FW0_AON_WTLCP_TDSP_CTRL0_RD_SEC            BIT(17)
#define BIT_REG_FW0_AON_WTLCP_LDSP_CTRL1_RD_SEC            BIT(16)
#define BIT_REG_FW0_AON_WTLCP_LDSP_CTRL0_RD_SEC            BIT(15)
#define BIT_REG_FW0_AON_AUDCP_CTRL_RD_SEC                  BIT(14)
#define BIT_REG_FW0_AON_AUDCP_DSP_CTRL1_RD_SEC             BIT(13)
#define BIT_REG_FW0_AON_AUDCP_DSP_CTRL0_RD_SEC             BIT(12)
#define BIT_REG_FW0_AON_CGM_CLK_TOP_REG1_RD_SEC            BIT(11)
#define BIT_REG_FW0_AON_CGM_REG1_RD_SEC                    BIT(10)
#define BIT_REG_FW0_AON_RC100M_CFG_RD_SEC                  BIT(9)
#define BIT_REG_FW0_AON_APB_RST3_RD_SEC                    BIT(8)
#define BIT_REG_FW0_AON_SP_CFG_BUS_RD_SEC                  BIT(7)
#define BIT_REG_FW0_AON_CGM_ESE_RD_SEC                     BIT(6)
#define BIT_REG_FW0_AON_APCPU_CLK_CTRL0_RD_SEC             BIT(5)
#define BIT_REG_FW0_AON_AUTO_GATE_CTRL3_RD_SEC             BIT(4)
#define BIT_REG_FW0_AON_AUTO_GATE_CTRL2_RD_SEC             BIT(3)
#define BIT_REG_FW0_AON_LVDSDIS_SEL_RD_SEC                 BIT(2)
#define BIT_REG_FW0_AON_PLL_BG_CFG_RD_SEC                  BIT(1)
#define BIT_REG_FW0_AON_CCIR_RCVR_CFG_RD_SEC               BIT(0)

/* REG_REG_FW0_AON_REG_RD_CTRL_2 */

#define BIT_REG_FW0_AON_APCPU_CLUSTER_APB_LPC_CTRL_RD_SEC  BIT(31)
#define BIT_REG_FW0_AON_APCPU_CLUSTER_ATB_LPC_CTRL_RD_SEC  BIT(30)
#define BIT_REG_FW0_AON_APCPU_GIC_COL_LP_CTRL_RD_SEC       BIT(29)
#define BIT_REG_FW0_AON_APCPU_DEBUG_PWR_LP_CTRL_RD_SEC     BIT(28)
#define BIT_REG_FW0_AON_APCPU_MONITOR_STATUS_RD_SEC        BIT(27)
#define BIT_REG_FW0_AON_AP_SIM_TOP_CTRL_RD_SEC             BIT(26)
#define BIT_REG_FW0_AON_PUBCP_SIM3_TOP_CTRL_RD_SEC         BIT(25)
#define BIT_REG_FW0_AON_PUBCP_SIM2_TOP_CTRL_RD_SEC         BIT(24)
#define BIT_REG_FW0_AON_PUBCP_SIM1_TOP_CTRL_RD_SEC         BIT(23)
#define BIT_REG_FW0_AON_OVERHEAT_CTRL_RD_SEC               BIT(22)
#define BIT_REG_FW0_AON_THM2_CTRL_RD_SEC                   BIT(21)
#define BIT_REG_FW0_AON_THM1_CTRL_RD_SEC                   BIT(20)
#define BIT_REG_FW0_AON_THM0_CTRL_RD_SEC                   BIT(19)
#define BIT_REG_FW0_AON_LVDSRF_CTRL_RD_SEC                 BIT(18)
#define BIT_REG_FW0_AON_USB_CLK_REF_SEL_RD_SEC             BIT(17)
#define BIT_REG_FW0_AON_OTG_CTRL1_RD_SEC                   BIT(16)
#define BIT_REG_FW0_AON_OTG_CTRL0_RD_SEC                   BIT(15)
#define BIT_REG_FW0_AON_OTG_PHY_CTRL_RD_SEC                BIT(14)
#define BIT_REG_FW0_AON_OTG_PHY_TEST_RD_SEC                BIT(13)
#define BIT_REG_FW0_AON_OTG_PHY_TUNE_RD_SEC                BIT(12)
#define BIT_REG_FW0_AON_MBIST_EFUSE_CTRL_RD_SEC            BIT(11)
#define BIT_REG_FW0_AON_PAD_DBG_BUS_SEL_CFG6_RD_SEC        BIT(10)
#define BIT_REG_FW0_AON_PAD_DBG_BUS_SEL_CFG5_RD_SEC        BIT(9)
#define BIT_REG_FW0_AON_PAD_DBG_BUS_SEL_CFG4_RD_SEC        BIT(8)
#define BIT_REG_FW0_AON_PAD_DBG_BUS_SEL_CFG3_RD_SEC        BIT(7)
#define BIT_REG_FW0_AON_PAD_DBG_BUS_SEL_CFG2_RD_SEC        BIT(6)
#define BIT_REG_FW0_AON_PAD_DBG_BUS_SEL_CFG1_RD_SEC        BIT(5)
#define BIT_REG_FW0_AON_SYS_DEBUG_BUS_SEL_CFG3_RD_SEC      BIT(4)
#define BIT_REG_FW0_AON_SYS_DEBUG_BUS_SEL_CFG2_RD_SEC      BIT(3)
#define BIT_REG_FW0_AON_SYS_DEBUG_BUS_SEL_CFG1_RD_SEC      BIT(2)
#define BIT_REG_FW0_AON_SYS_DEBUG_BUS_SEL_CFG0_RD_SEC      BIT(1)
#define BIT_REG_FW0_AON_DBG_DJTAG_CTRL_RD_SEC              BIT(0)

/* REG_REG_FW0_AON_REG_RD_CTRL_3 */

#define BIT_REG_FW0_AON_AON_MTX_S8_LPC_CTRL_RD_SEC         BIT(31)
#define BIT_REG_FW0_AON_AON_MTX_S7_LPC_CTRL_RD_SEC         BIT(30)
#define BIT_REG_FW0_AON_AON_MTX_S6_LPC_CTRL_RD_SEC         BIT(29)
#define BIT_REG_FW0_AON_AON_MTX_S5_LPC_CTRL_RD_SEC         BIT(28)
#define BIT_REG_FW0_AON_AON_MTX_S4_LPC_CTRL_RD_SEC         BIT(27)
#define BIT_REG_FW0_AON_AON_MTX_S3_LPC_CTRL_RD_SEC         BIT(26)
#define BIT_REG_FW0_AON_AON_MTX_S2_LPC_CTRL_RD_SEC         BIT(25)
#define BIT_REG_FW0_AON_AON_MTX_S1_LPC_CTRL_RD_SEC         BIT(24)
#define BIT_REG_FW0_AON_AON_MTX_S0_LPC_CTRL_RD_SEC         BIT(23)
#define BIT_REG_FW0_AON_AON_MTX_M6_LPC_CTRL_RD_SEC         BIT(22)
#define BIT_REG_FW0_AON_AON_MTX_M5_LPC_CTRL_RD_SEC         BIT(21)
#define BIT_REG_FW0_AON_AON_MTX_M4_LPC_CTRL_RD_SEC         BIT(20)
#define BIT_REG_FW0_AON_AON_MTX_M3_LPC_CTRL_RD_SEC         BIT(19)
#define BIT_REG_FW0_AON_AON_MTX_M2_LPC_CTRL_RD_SEC         BIT(18)
#define BIT_REG_FW0_AON_AON_MTX_M1_LPC_CTRL_RD_SEC         BIT(17)
#define BIT_REG_FW0_AON_AON_MTX_M0_LPC_CTRL_RD_SEC         BIT(16)
#define BIT_REG_FW0_AON_AON_MTX_MAIN_LPC_CTRL_RD_SEC       BIT(15)
#define BIT_REG_FW0_AON_CM42AON_LPC_CTRL_RD_SEC            BIT(14)
#define BIT_REG_FW0_AON_DDRPHY_VREP_RD_SEC                 BIT(13)
#define BIT_REG_FW0_AON_PUB_CLK_GATING_CTRL_RD_SEC         BIT(12)
#define BIT_REG_FW0_AON_DPLL_CTRL_RD_SEC                   BIT(11)
#define BIT_REG_FW0_AON_MPLL3_CTRL_RD_SEC                  BIT(10)
#define BIT_REG_FW0_AON_MPLL2_CTRL_RD_SEC                  BIT(9)
#define BIT_REG_FW0_AON_MPLL1_CTRL_RD_SEC                  BIT(8)
#define BIT_REG_FW0_AON_MPLL0_CTRL_RD_SEC                  BIT(7)
#define BIT_REG_FW0_AON_APCPU_QOS_CTRL_RD_SEC              BIT(6)
#define BIT_REG_FW0_AON_APCPU_DDR_AB_LPC_CTRL_RD_SEC       BIT(5)
#define BIT_REG_FW0_AON_APCPU_CLUSTER_SCU_LPC_CTRL_RD_SEC  BIT(4)
#define BIT_REG_FW0_AON_APCPU_TOP_MTX_M0_LPC_CTRL_RD_SEC   BIT(3)
#define BIT_REG_FW0_AON_APCPU_DBG_BLK_LPC_CTRL_RD_SEC      BIT(2)
#define BIT_REG_FW0_AON_APCPU_GIC600_GIC_LPC_CTRL_RD_SEC   BIT(1)
#define BIT_REG_FW0_AON_APCPU_CLUSTER_GIC_LPC_CTRL_RD_SEC  BIT(0)

/* REG_REG_FW0_AON_REG_RD_CTRL_4 */

#define BIT_REG_FW0_AON_AON_SDIO_RD_SEC                    BIT(31)
#define BIT_REG_FW0_AON_CGM_RESCUE_RD_SEC                  BIT(30)
#define BIT_REG_FW0_AON_FUNC_TEST_BOOT_ADDR_RD_SEC         BIT(29)
#define BIT_REG_FW0_AON_LEAKAGE_SWITCH_RD_SEC              BIT(28)
#define BIT_REG_FW0_AON_LEAKAGE_MAGIC_WORD_RD_SEC          BIT(27)
#define BIT_REG_FW0_AON_DEBUG_FILTER_5_RD_SEC              BIT(26)
#define BIT_REG_FW0_AON_DEBUG_FILTER_4_RD_SEC              BIT(25)
#define BIT_REG_FW0_AON_DEBUG_FILTER_3_RD_SEC              BIT(24)
#define BIT_REG_FW0_AON_DEBUG_FILTER_2_RD_SEC              BIT(23)
#define BIT_REG_FW0_AON_DEBUG_FILTER_1_RD_SEC              BIT(22)
#define BIT_REG_FW0_AON_DEBUG_FILTER_0_RD_SEC              BIT(21)
#define BIT_REG_FW0_AON_PLL_LOCK_OUT_SEL_RD_SEC            BIT(20)
#define BIT_REG_FW0_AON_AON_MTX_PROT_CFG_RD_SEC            BIT(19)
#define BIT_REG_FW0_AON_RES_REG1_RD_SEC                    BIT(18)
#define BIT_REG_FW0_AON_RES_REG0_RD_SEC                    BIT(17)
#define BIT_REG_FW0_AON_DEVICE_LIFE_CYCLE_RD_SEC           BIT(16)
#define BIT_REG_FW0_AON_BOND_OPT0_RD_SEC                   BIT(15)
#define BIT_REG_FW0_AON_WDG_RST_FLAG_RD_SEC                BIT(14)
#define BIT_REG_FW0_AON_APCPU_INT_ENABLE_CTRL5_RD_SEC      BIT(13)
#define BIT_REG_FW0_AON_APCPU_INT_ENABLE_CTRL4_RD_SEC      BIT(12)
#define BIT_REG_FW0_AON_APCPU_INT_ENABLE_CTRL3_RD_SEC      BIT(11)
#define BIT_REG_FW0_AON_APCPU_INT_ENABLE_CTRL2_RD_SEC      BIT(10)
#define BIT_REG_FW0_AON_APCPU_INT_ENABLE_CTRL1_RD_SEC      BIT(9)
#define BIT_REG_FW0_AON_APCPU_INT_ENABLE_CTRL0_RD_SEC      BIT(8)
#define BIT_REG_FW0_AON_MIPI_CSI_POWER_CTRL_RD_SEC         BIT(7)
#define BIT_REG_FW0_AON_AON_APB_FREQ_CTRL_RD_SEC           BIT(6)
#define BIT_REG_FW0_AON_PUBCP2WTLCP_SLI_LPC_CTRL_RD_SEC    BIT(5)
#define BIT_REG_FW0_AON_AON2DDR_BRG_LPC_CTRL_RD_SEC        BIT(4)
#define BIT_REG_FW0_AON_APCPU2DDR_SLI_LPC_CTRL_RD_SEC      BIT(3)
#define BIT_REG_FW0_AON_AUDCP2DDR_SLI_LPC_CTRL_RD_SEC      BIT(2)
#define BIT_REG_FW0_AON_WTLCP2DDR_SLI_LPC_CTRL_RD_SEC      BIT(1)
#define BIT_REG_FW0_AON_AON_MTX_S9_LPC_CTRL_RD_SEC         BIT(0)

/* REG_REG_FW0_AON_REG_RD_CTRL_5 */

#define BIT_REG_FW0_AON_AON_FUNC_CTRL_1_RD_SEC             BIT(8)
#define BIT_REG_FW0_AON_AON_FUNC_CTRL_0_RD_SEC             BIT(7)
#define BIT_REG_FW0_AON_SCC_DBG_BUS_RD_SEC                 BIT(6)
#define BIT_REG_FW0_AON_DBG_BUS_DATA_AUDCP_RD_SEC          BIT(5)
#define BIT_REG_FW0_AON_DBG_BUS_DATA_PUBCP_RD_SEC          BIT(4)
#define BIT_REG_FW0_AON_DBG_BUS_DATA_WTLCP_RD_SEC          BIT(3)
#define BIT_REG_FW0_AON_SP_WAKEUP_MASK_EN2_RD_SEC          BIT(2)
#define BIT_REG_FW0_AON_SP_WAKEUP_MASK_EN1_RD_SEC          BIT(1)
#define BIT_REG_FW0_AON_SP_WAKEUP_MASK_EN0_RD_SEC          BIT(0)

/* REG_REG_FW0_AON_REG_WR_CTRL_0 */

#define BIT_REG_FW0_AON_AON_CHIP_ID_WR_SEC                 BIT(31)
#define BIT_REG_FW0_AON_AON_VER_ID_WR_SEC                  BIT(30)
#define BIT_REG_FW0_AON_AON_MFT_ID_WR_SEC                  BIT(29)
#define BIT_REG_FW0_AON_AON_IMPL_ID_WR_SEC                 BIT(28)
#define BIT_REG_FW0_AON_AON_PLAT_ID1_WR_SEC                BIT(27)
#define BIT_REG_FW0_AON_AON_PLAT_ID0_WR_SEC                BIT(26)
#define BIT_REG_FW0_AON_AON_CHIP_ID1_WR_SEC                BIT(25)
#define BIT_REG_FW0_AON_AON_CHIP_ID0_WR_SEC                BIT(24)
#define BIT_REG_FW0_AON_AP_AXI_CTRL_WR_SEC                 BIT(23)
#define BIT_REG_FW0_AON_AUTO_GATE_CTRL1_WR_SEC             BIT(22)
#define BIT_REG_FW0_AON_AUTO_GATE_CTRL0_WR_SEC             BIT(21)
#define BIT_REG_FW0_AON_MDAR_SYS_HSDL_CFG_WR_SEC           BIT(20)
#define BIT_REG_FW0_AON_CM4_SYS_SOFT_RST_WR_SEC            BIT(19)
#define BIT_REG_FW0_AON_USER_RSV_FLAG1_WR_SEC              BIT(18)
#define BIT_REG_FW0_AON_DAP_DJTAG_SEL_WR_SEC               BIT(17)
#define BIT_REG_FW0_AON_AON_APB_CLK_SEL_WR_SEC             BIT(16)
#define BIT_REG_FW0_AON_AON_REG_PROT_WR_SEC                BIT(15)
#define BIT_REG_FW0_AON_AUDCP_BOOT_PROT_WR_SEC             BIT(14)
#define BIT_REG_FW0_AON_DCXO_LC_REG1_WR_SEC                BIT(13)
#define BIT_REG_FW0_AON_DCXO_LC_REG0_WR_SEC                BIT(12)
#define BIT_REG_FW0_AON_CP_ARM_JTAG_CTRL_WR_SEC            BIT(11)
#define BIT_REG_FW0_AON_BB_BG_CTRL_WR_SEC                  BIT(10)
#define BIT_REG_FW0_AON_BOOT_MODE_WR_SEC                   BIT(9)
#define BIT_REG_FW0_AON_TS_CFG_WR_SEC                      BIT(8)
#define BIT_REG_FW0_AON_PWR_CTRL_WR_SEC                    BIT(7)
#define BIT_REG_FW0_AON_APB_RTC_EB0_WR_SEC                 BIT(6)
#define BIT_REG_FW0_AON_APB_RST2_WR_SEC                    BIT(5)
#define BIT_REG_FW0_AON_APB_RST1_WR_SEC                    BIT(4)
#define BIT_REG_FW0_AON_APB_RST0_WR_SEC                    BIT(3)
#define BIT_REG_FW0_AON_APB_EB2_WR_SEC                     BIT(2)
#define BIT_REG_FW0_AON_APB_EB1_WR_SEC                     BIT(1)
#define BIT_REG_FW0_AON_APB_EB0_WR_SEC                     BIT(0)

/* REG_REG_FW0_AON_REG_WR_CTRL_1 */

#define BIT_REG_FW0_AON_EB_AON_ADD1_WR_SEC                 BIT(31)
#define BIT_REG_FW0_AON_VDSP_INT_CTRL_WR_SEC               BIT(30)
#define BIT_REG_FW0_AON_SOFT_RST_AON_ADD1_WR_SEC           BIT(29)
#define BIT_REG_FW0_AON_ESE_INT_MASK_WR_SEC                BIT(28)
#define BIT_REG_FW0_AON_AON_SOC_USB_CTRL_WR_SEC            BIT(27)
#define BIT_REG_FW0_AON_PUBCP_LPC_CTRL_WR_SEC              BIT(26)
#define BIT_REG_FW0_AON_WTLCP_LPC_CTRL_WR_SEC              BIT(25)
#define BIT_REG_FW0_AON_VECTOR_VDSP_WR_SEC                 BIT(24)
#define BIT_REG_FW0_AON_PUBCP_CTRL_WR_SEC                  BIT(23)
#define BIT_REG_FW0_AON_PCP_SOFT_RST_WR_SEC                BIT(22)
#define BIT_REG_FW0_AON_PCP_AON_EB_WR_SEC                  BIT(21)
#define BIT_REG_FW0_AON_WTL_WCDMA_EB_WR_SEC                BIT(20)
#define BIT_REG_FW0_AON_WTLCP_CTRL_WR_SEC                  BIT(19)
#define BIT_REG_FW0_AON_WTLCP_TDSP_CTRL1_WR_SEC            BIT(18)
#define BIT_REG_FW0_AON_WTLCP_TDSP_CTRL0_WR_SEC            BIT(17)
#define BIT_REG_FW0_AON_WTLCP_LDSP_CTRL1_WR_SEC            BIT(16)
#define BIT_REG_FW0_AON_WTLCP_LDSP_CTRL0_WR_SEC            BIT(15)
#define BIT_REG_FW0_AON_AUDCP_CTRL_WR_SEC                  BIT(14)
#define BIT_REG_FW0_AON_AUDCP_DSP_CTRL1_WR_SEC             BIT(13)
#define BIT_REG_FW0_AON_AUDCP_DSP_CTRL0_WR_SEC             BIT(12)
#define BIT_REG_FW0_AON_CGM_CLK_TOP_REG1_WR_SEC            BIT(11)
#define BIT_REG_FW0_AON_CGM_REG1_WR_SEC                    BIT(10)
#define BIT_REG_FW0_AON_RC100M_CFG_WR_SEC                  BIT(9)
#define BIT_REG_FW0_AON_APB_RST3_WR_SEC                    BIT(8)
#define BIT_REG_FW0_AON_SP_CFG_BUS_WR_SEC                  BIT(7)
#define BIT_REG_FW0_AON_CGM_ESE_WR_SEC                     BIT(6)
#define BIT_REG_FW0_AON_APCPU_CLK_CTRL0_WR_SEC             BIT(5)
#define BIT_REG_FW0_AON_AUTO_GATE_CTRL3_WR_SEC             BIT(4)
#define BIT_REG_FW0_AON_AUTO_GATE_CTRL2_WR_SEC             BIT(3)
#define BIT_REG_FW0_AON_LVDSDIS_SEL_WR_SEC                 BIT(2)
#define BIT_REG_FW0_AON_PLL_BG_CFG_WR_SEC                  BIT(1)
#define BIT_REG_FW0_AON_CCIR_RCVR_CFG_WR_SEC               BIT(0)

/* REG_REG_FW0_AON_REG_WR_CTRL_2 */

#define BIT_REG_FW0_AON_APCPU_CLUSTER_APB_LPC_CTRL_WR_SEC  BIT(31)
#define BIT_REG_FW0_AON_APCPU_CLUSTER_ATB_LPC_CTRL_WR_SEC  BIT(30)
#define BIT_REG_FW0_AON_APCPU_GIC_COL_LP_CTRL_WR_SEC       BIT(29)
#define BIT_REG_FW0_AON_APCPU_DEBUG_PWR_LP_CTRL_WR_SEC     BIT(28)
#define BIT_REG_FW0_AON_APCPU_MONITOR_STATUS_WR_SEC        BIT(27)
#define BIT_REG_FW0_AON_AP_SIM_TOP_CTRL_WR_SEC             BIT(26)
#define BIT_REG_FW0_AON_PUBCP_SIM3_TOP_CTRL_WR_SEC         BIT(25)
#define BIT_REG_FW0_AON_PUBCP_SIM2_TOP_CTRL_WR_SEC         BIT(24)
#define BIT_REG_FW0_AON_PUBCP_SIM1_TOP_CTRL_WR_SEC         BIT(23)
#define BIT_REG_FW0_AON_OVERHEAT_CTRL_WR_SEC               BIT(22)
#define BIT_REG_FW0_AON_THM2_CTRL_WR_SEC                   BIT(21)
#define BIT_REG_FW0_AON_THM1_CTRL_WR_SEC                   BIT(20)
#define BIT_REG_FW0_AON_THM0_CTRL_WR_SEC                   BIT(19)
#define BIT_REG_FW0_AON_LVDSRF_CTRL_WR_SEC                 BIT(18)
#define BIT_REG_FW0_AON_USB_CLK_REF_SEL_WR_SEC             BIT(17)
#define BIT_REG_FW0_AON_OTG_CTRL1_WR_SEC                   BIT(16)
#define BIT_REG_FW0_AON_OTG_CTRL0_WR_SEC                   BIT(15)
#define BIT_REG_FW0_AON_OTG_PHY_CTRL_WR_SEC                BIT(14)
#define BIT_REG_FW0_AON_OTG_PHY_TEST_WR_SEC                BIT(13)
#define BIT_REG_FW0_AON_OTG_PHY_TUNE_WR_SEC                BIT(12)
#define BIT_REG_FW0_AON_MBIST_EFUSE_CTRL_WR_SEC            BIT(11)
#define BIT_REG_FW0_AON_PAD_DBG_BUS_SEL_CFG6_WR_SEC        BIT(10)
#define BIT_REG_FW0_AON_PAD_DBG_BUS_SEL_CFG5_WR_SEC        BIT(9)
#define BIT_REG_FW0_AON_PAD_DBG_BUS_SEL_CFG4_WR_SEC        BIT(8)
#define BIT_REG_FW0_AON_PAD_DBG_BUS_SEL_CFG3_WR_SEC        BIT(7)
#define BIT_REG_FW0_AON_PAD_DBG_BUS_SEL_CFG2_WR_SEC        BIT(6)
#define BIT_REG_FW0_AON_PAD_DBG_BUS_SEL_CFG1_WR_SEC        BIT(5)
#define BIT_REG_FW0_AON_SYS_DEBUG_BUS_SEL_CFG3_WR_SEC      BIT(4)
#define BIT_REG_FW0_AON_SYS_DEBUG_BUS_SEL_CFG2_WR_SEC      BIT(3)
#define BIT_REG_FW0_AON_SYS_DEBUG_BUS_SEL_CFG1_WR_SEC      BIT(2)
#define BIT_REG_FW0_AON_SYS_DEBUG_BUS_SEL_CFG0_WR_SEC      BIT(1)
#define BIT_REG_FW0_AON_DBG_DJTAG_CTRL_WR_SEC              BIT(0)

/* REG_REG_FW0_AON_REG_WR_CTRL_3 */

#define BIT_REG_FW0_AON_AON_MTX_S8_LPC_CTRL_WR_SEC         BIT(31)
#define BIT_REG_FW0_AON_AON_MTX_S7_LPC_CTRL_WR_SEC         BIT(30)
#define BIT_REG_FW0_AON_AON_MTX_S6_LPC_CTRL_WR_SEC         BIT(29)
#define BIT_REG_FW0_AON_AON_MTX_S5_LPC_CTRL_WR_SEC         BIT(28)
#define BIT_REG_FW0_AON_AON_MTX_S4_LPC_CTRL_WR_SEC         BIT(27)
#define BIT_REG_FW0_AON_AON_MTX_S3_LPC_CTRL_WR_SEC         BIT(26)
#define BIT_REG_FW0_AON_AON_MTX_S2_LPC_CTRL_WR_SEC         BIT(25)
#define BIT_REG_FW0_AON_AON_MTX_S1_LPC_CTRL_WR_SEC         BIT(24)
#define BIT_REG_FW0_AON_AON_MTX_S0_LPC_CTRL_WR_SEC         BIT(23)
#define BIT_REG_FW0_AON_AON_MTX_M6_LPC_CTRL_WR_SEC         BIT(22)
#define BIT_REG_FW0_AON_AON_MTX_M5_LPC_CTRL_WR_SEC         BIT(21)
#define BIT_REG_FW0_AON_AON_MTX_M4_LPC_CTRL_WR_SEC         BIT(20)
#define BIT_REG_FW0_AON_AON_MTX_M3_LPC_CTRL_WR_SEC         BIT(19)
#define BIT_REG_FW0_AON_AON_MTX_M2_LPC_CTRL_WR_SEC         BIT(18)
#define BIT_REG_FW0_AON_AON_MTX_M1_LPC_CTRL_WR_SEC         BIT(17)
#define BIT_REG_FW0_AON_AON_MTX_M0_LPC_CTRL_WR_SEC         BIT(16)
#define BIT_REG_FW0_AON_AON_MTX_MAIN_LPC_CTRL_WR_SEC       BIT(15)
#define BIT_REG_FW0_AON_CM42AON_LPC_CTRL_WR_SEC            BIT(14)
#define BIT_REG_FW0_AON_DDRPHY_VREP_WR_SEC                 BIT(13)
#define BIT_REG_FW0_AON_PUB_CLK_GATING_CTRL_WR_SEC         BIT(12)
#define BIT_REG_FW0_AON_DPLL_CTRL_WR_SEC                   BIT(11)
#define BIT_REG_FW0_AON_MPLL3_CTRL_WR_SEC                  BIT(10)
#define BIT_REG_FW0_AON_MPLL2_CTRL_WR_SEC                  BIT(9)
#define BIT_REG_FW0_AON_MPLL1_CTRL_WR_SEC                  BIT(8)
#define BIT_REG_FW0_AON_MPLL0_CTRL_WR_SEC                  BIT(7)
#define BIT_REG_FW0_AON_APCPU_QOS_CTRL_WR_SEC              BIT(6)
#define BIT_REG_FW0_AON_APCPU_DDR_AB_LPC_CTRL_WR_SEC       BIT(5)
#define BIT_REG_FW0_AON_APCPU_CLUSTER_SCU_LPC_CTRL_WR_SEC  BIT(4)
#define BIT_REG_FW0_AON_APCPU_TOP_MTX_M0_LPC_CTRL_WR_SEC   BIT(3)
#define BIT_REG_FW0_AON_APCPU_DBG_BLK_LPC_CTRL_WR_SEC      BIT(2)
#define BIT_REG_FW0_AON_APCPU_GIC600_GIC_LPC_CTRL_WR_SEC   BIT(1)
#define BIT_REG_FW0_AON_APCPU_CLUSTER_GIC_LPC_CTRL_WR_SEC  BIT(0)

/* REG_REG_FW0_AON_REG_WR_CTRL_4 */

#define BIT_REG_FW0_AON_AON_SDIO_WR_SEC                    BIT(31)
#define BIT_REG_FW0_AON_CGM_RESCUE_WR_SEC                  BIT(30)
#define BIT_REG_FW0_AON_FUNC_TEST_BOOT_ADDR_WR_SEC         BIT(29)
#define BIT_REG_FW0_AON_LEAKAGE_SWITCH_WR_SEC              BIT(28)
#define BIT_REG_FW0_AON_LEAKAGE_MAGIC_WORD_WR_SEC          BIT(27)
#define BIT_REG_FW0_AON_DEBUG_FILTER_5_WR_SEC              BIT(26)
#define BIT_REG_FW0_AON_DEBUG_FILTER_4_WR_SEC              BIT(25)
#define BIT_REG_FW0_AON_DEBUG_FILTER_3_WR_SEC              BIT(24)
#define BIT_REG_FW0_AON_DEBUG_FILTER_2_WR_SEC              BIT(23)
#define BIT_REG_FW0_AON_DEBUG_FILTER_1_WR_SEC              BIT(22)
#define BIT_REG_FW0_AON_DEBUG_FILTER_0_WR_SEC              BIT(21)
#define BIT_REG_FW0_AON_PLL_LOCK_OUT_SEL_WR_SEC            BIT(20)
#define BIT_REG_FW0_AON_AON_MTX_PROT_CFG_WR_SEC            BIT(19)
#define BIT_REG_FW0_AON_RES_REG1_WR_SEC                    BIT(18)
#define BIT_REG_FW0_AON_RES_REG0_WR_SEC                    BIT(17)
#define BIT_REG_FW0_AON_DEVICE_LIFE_CYCLE_WR_SEC           BIT(16)
#define BIT_REG_FW0_AON_BOND_OPT0_WR_SEC                   BIT(15)
#define BIT_REG_FW0_AON_WDG_RST_FLAG_WR_SEC                BIT(14)
#define BIT_REG_FW0_AON_APCPU_INT_ENABLE_CTRL5_WR_SEC      BIT(13)
#define BIT_REG_FW0_AON_APCPU_INT_ENABLE_CTRL4_WR_SEC      BIT(12)
#define BIT_REG_FW0_AON_APCPU_INT_ENABLE_CTRL3_WR_SEC      BIT(11)
#define BIT_REG_FW0_AON_APCPU_INT_ENABLE_CTRL2_WR_SEC      BIT(10)
#define BIT_REG_FW0_AON_APCPU_INT_ENABLE_CTRL1_WR_SEC      BIT(9)
#define BIT_REG_FW0_AON_APCPU_INT_ENABLE_CTRL0_WR_SEC      BIT(8)
#define BIT_REG_FW0_AON_MIPI_CSI_POWER_CTRL_WR_SEC         BIT(7)
#define BIT_REG_FW0_AON_AON_APB_FREQ_CTRL_WR_SEC           BIT(6)
#define BIT_REG_FW0_AON_PUBCP2WTLCP_SLI_LPC_CTRL_WR_SEC    BIT(5)
#define BIT_REG_FW0_AON_AON2DDR_BRG_LPC_CTRL_WR_SEC        BIT(4)
#define BIT_REG_FW0_AON_APCPU2DDR_SLI_LPC_CTRL_WR_SEC      BIT(3)
#define BIT_REG_FW0_AON_AUDCP2DDR_SLI_LPC_CTRL_WR_SEC      BIT(2)
#define BIT_REG_FW0_AON_WTLCP2DDR_SLI_LPC_CTRL_WR_SEC      BIT(1)
#define BIT_REG_FW0_AON_AON_MTX_S9_LPC_CTRL_WR_SEC         BIT(0)

/* REG_REG_FW0_AON_REG_WR_CTRL_5 */

#define BIT_REG_FW0_AON_AON_FUNC_CTRL_1_WR_SEC             BIT(8)
#define BIT_REG_FW0_AON_AON_FUNC_CTRL_0_WR_SEC             BIT(7)
#define BIT_REG_FW0_AON_SCC_DBG_BUS_WR_SEC                 BIT(6)
#define BIT_REG_FW0_AON_DBG_BUS_DATA_AUDCP_WR_SEC          BIT(5)
#define BIT_REG_FW0_AON_DBG_BUS_DATA_PUBCP_WR_SEC          BIT(4)
#define BIT_REG_FW0_AON_DBG_BUS_DATA_WTLCP_WR_SEC          BIT(3)
#define BIT_REG_FW0_AON_SP_WAKEUP_MASK_EN2_WR_SEC          BIT(2)
#define BIT_REG_FW0_AON_SP_WAKEUP_MASK_EN1_WR_SEC          BIT(1)
#define BIT_REG_FW0_AON_SP_WAKEUP_MASK_EN0_WR_SEC          BIT(0)

/* REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY0 */

#define BIT_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY0(x)            (((x) & 0xFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY1 */

#define BIT_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY1(x)            (((x) & 0xFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY2 */

#define BIT_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY2(x)            (((x) & 0xFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY3 */

#define BIT_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY3(x)            (((x) & 0xFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY4 */

#define BIT_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY4(x)            (((x) & 0xFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY5 */

#define BIT_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY5(x)            (((x) & 0xFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY6 */

#define BIT_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY6(x)            (((x) & 0xFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY7 */

#define BIT_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY7(x)            (((x) & 0xFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY8 */

#define BIT_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY8(x)            (((x) & 0xFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY9 */

#define BIT_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY9(x)            (((x) & 0xFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY10 */

#define BIT_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY10(x)           (((x) & 0xFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY11 */

#define BIT_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY11(x)           (((x) & 0xFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY12 */

#define BIT_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY12(x)           (((x) & 0xFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY13 */

#define BIT_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY13(x)           (((x) & 0xFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY14 */

#define BIT_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY14(x)           (((x) & 0xFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY15 */

#define BIT_REG_FW0_AON_BIT_CTRL_ADDR_ARRAY15(x)           (((x) & 0xFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ARRAY0 */

#define BIT_REG_FW0_AON_BIT_CTRL_ARRAY0(x)                 (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ARRAY1 */

#define BIT_REG_FW0_AON_BIT_CTRL_ARRAY1(x)                 (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ARRAY2 */

#define BIT_REG_FW0_AON_BIT_CTRL_ARRAY2(x)                 (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ARRAY3 */

#define BIT_REG_FW0_AON_BIT_CTRL_ARRAY3(x)                 (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ARRAY4 */

#define BIT_REG_FW0_AON_BIT_CTRL_ARRAY4(x)                 (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ARRAY5 */

#define BIT_REG_FW0_AON_BIT_CTRL_ARRAY5(x)                 (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ARRAY6 */

#define BIT_REG_FW0_AON_BIT_CTRL_ARRAY6(x)                 (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ARRAY7 */

#define BIT_REG_FW0_AON_BIT_CTRL_ARRAY7(x)                 (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ARRAY8 */

#define BIT_REG_FW0_AON_BIT_CTRL_ARRAY8(x)                 (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ARRAY9 */

#define BIT_REG_FW0_AON_BIT_CTRL_ARRAY9(x)                 (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ARRAY10 */

#define BIT_REG_FW0_AON_BIT_CTRL_ARRAY10(x)                (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ARRAY11 */

#define BIT_REG_FW0_AON_BIT_CTRL_ARRAY11(x)                (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ARRAY12 */

#define BIT_REG_FW0_AON_BIT_CTRL_ARRAY12(x)                (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ARRAY13 */

#define BIT_REG_FW0_AON_BIT_CTRL_ARRAY13(x)                (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ARRAY14 */

#define BIT_REG_FW0_AON_BIT_CTRL_ARRAY14(x)                (((x) & 0xFFFFFFFF))

/* REG_REG_FW0_AON_BIT_CTRL_ARRAY15 */

#define BIT_REG_FW0_AON_BIT_CTRL_ARRAY15(x)                (((x) & 0xFFFFFFFF))


#endif /* REG_FW0_AON_H */


